MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) One-shot pulse mode [10]
Figure 28 shows the bit configuration of the timer Ai mode register
during one-shot pulse mode. In one-shot pulse mode, bit 0 and bit 5
must be “0” and bit 1 and bit 2 must be “1”.
The trigger is enabled when the count start bit is “1”. The trigger can
be generated by software or it can be input from the TAiIN pin. Soft-
ware trigger is selected when bit 4 is “0” and the input signal from the
TAiIN pin is used as the trigger when it is “1“.
Addresses
5616
5716
5816
5916
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
7
6
5
0
4
3
2
1
1
1
0
0
5A16
Bit 3 is used to determine whether to trigger at the fall of the trigger
signal or at the rise. The trigger is at the fall of the trigger signal when
bit 3 is “0” and at the rise of the trigger signal when it is “1”.
Software trigger is generated by setting the bit in the one-shot start
bit corresponding to each timer.
1 0 : Always “10” in one-shot pulse mode
1 : Always “1” in one-shot pulse mode
0 × : Software trigger
1 0 : Trigger at the falling edge of TAiIN
input
1 1 : Trigger at the rising edge of TAiIN
input
0 : Always “0” in one-shot pulse mode
Figure 29 shows the bit configuration of the one-shot start register.
As shown in Figure 30, when a trigger signal is received, the counter
counts the clock selected by bits 6 and 7.
If the contents of the counter is not 000016, the TAiOUT pin goes “H”
when a trigger signal is received. The count direction is decrement.
When the counter reaches 000116, The TAiOUT pin goes “L” and
count is stopped. The contents of the reload register is transferred to
the counter. At the same time, an interrupt request signal is gener-
ated and the interrupt request bit in the timer Ai interrupt control reg-
ister is set. This is repeated each time a trigger signal is received.
The output pulse width is
Clock source select
0 0 : Select Pf2
0 1 : Select Pf16
1 0 : Select Pf64
1 1 : Select Pf512
1
pulse frequency of the selected clock
× (counter’s value at the time of trigger).
Fig. 28 Timer Ai mode register bit configuration during one-shot
pulse mode
If the count start flag is “0”, TAiOUT goes “L”. Therefore, the value
corresponding to the desired pulse width must be written to timer Ai
before setting the timer Ai count start bit.
As shown in Figure 31, a trigger signal can be received before the
operation for the previous trigger signal is completed. In this case,
the contents of the reload register is transferred to the counter by the
trigger and then that value is decremented.
Except when retriggering while operating, the contents of the reload
register is not transferred to the counter by triggering.
When retriggering, there must be at least one timer count source
cycle before a new trigger can be issued.
Address
4216
7
6 5 4 3 2 1 0
One-shot start register
Timer A0 one-shot start bit
Timer A1 one-shot start bit
Timer A2 one-shot start bit
Timer A3 one-shot start bit
Timer A4 one-shot start bit
Data write is performed in the same way as for timer mode.
When data is written in timer Ai halted, it is also written to the reload
register and the counter.
When data is written to timer Ai which is busy, the data is written to
the reload register, but not to the counter. The counter is reloaded
with new data from the reload register at the next reload time.
Undefined data is read when timer Ai is read.
Fig. 29 One-shot start register bit configuration
29
RENESAS [ RENESAS TECHNOLOGY CORP ]
