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M37754S4CGP 参数 Datasheet PDF下载

M37754S4CGP图片预览
型号: M37754S4CGP
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片16位CMOS微机 [SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER]
分类和应用: 微控制器和处理器外围集成电路计算机时钟
文件页数/大小: 115 页 / 1558 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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MITSUBISHI MICROCOMPUTERS  
M37754M8C-XXXGP, M37754M8C-XXXHP  
M37754S4CGP, M37754S4CHP  
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER  
As shown in Figure 19, the timer Bi count start bit is at the same ad-  
dress as the timer Ai count start bit. The count is decremented, an  
TIMER B  
Figure 35 shows a block diagram of timer B.  
interrupt occurs, and the interrupt request bit in the timer Bi interrupt  
control register is set when the contents becomes 000016. At the  
same time, the contents of the reload register is stored in the counter  
and count is continued.  
Timer B has three modes: timer mode, event counter mode, and  
pulse period measurement/pulse width measurement mode. The  
mode is selected with bits 0 and 1 of the timer Bi mode register (i=0  
to 2). Each of these modes is described below.  
(1) Timer mode [00]  
Figure 36 shows the bit configuration of the timer Bi mode register  
during timer mode. Bits 0 and 1 of the timer Bi mode register must  
always be “0” in timer mode.  
Timer Bi does not have a pulse output function or a gate function like  
timer A.  
When data is written to timer Bi halted, it is written to the reload reg-  
ister and the counter. When data is written to timer Bi which is busy,  
the data is written to the reload register, but not to the counter. The  
new data is reloaded from the reload register to the counter at the  
next reload time and counting continues.  
Bits 6 and 7 are used to select the clock source. The counting of the  
selected clock starts when the count start bit is “1” and stops when  
“0”.  
The contents of the counter can be read at any time.  
Data bus
D
8 bits)  
(Higher 8 bits)  
Clock source selection  
• Timer  
Pf2  
• Pulse period measurement/Pulse  
width measurement  
ad register (16)  
Pf16  
Pf64  
Pf512  
Addresses  
Counter (16)  
Timer B0 5116 5016  
Timer B1 5316 5216  
Timer B2 5516 5416  
Polarity selection  
and edge pulse  
generator  
Event counter  
TBiIN  
(i = 0 – 2)  
start bit  
(4016)  
Counter reset  
circuit  
Note: Perform write and read Bi register in the condition of 16-bit data length : data length flag (m) =“0”.  
Fig. 35 Timer B block diagram  
33  
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