PR
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.
tion change
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pec bject to
al s su
e
a fin
not imits ar
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l
This entic
m
ice:
Not e para
Som
M
ELI
ARY
IN
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
s
SFR1 area (addresses E0
16
to FF
16
)
Bit allocation
:
Name
State immediately after reset
0 : “0” immediately after reset
1 : “1” immediately after reset
? : Indeterminate immediately
after reset
Function bit
:
:
No function bit
0 : Fix to this bit to “0”
(do not write to “1”)
1 : Fix to this bit to “1”
(do not write to “0”)
Address
E0
16
E1
16
E2
16
E3
16
E4
16
E5
16
E6
16
E7
16
E8
16
E9
16
EA
16
EB
16
EC
16
ED
16
EE
16
EF
16
F0
16
F1
16
F2
16
F3
16
F4
16
F5
16
F6
16
F7
16
F8
16
F9
16
FA
16
FB
16
FC
16
FD
16
FE
16
FF
16
Register
b7
Data slicer control register 1 (DSC1)
Data slicer control register 2 (DSC2)
Caption data register 1 (CD1)
Caption data register 2 (CD2)
Caption data register 3 (CD3)
Caption data register 4 (CD4)
Caption Position register (CPS)
Data slicer test register 2
Data slicer test register 1
Sync signal counter register (HC)
Clock run-in detect register (CRD)
Data clock position register (DPS)
Bit allocation
0
0
0
0
0
0
DSC12 DSC11 DSC10
State immediately after reset
b0 b7
b0
DSC25 DSC24 DSC23
0
DSC20
?
0
?
CDL17 CDL16 CDL15 CDL14 CDL13 CDL12 CDL11 CDL10
CDH17 CDH16 CDH15 CDH14 CDH13 CDH12 CDH11 CDH10
CDL27 CDL26 CDL25 CDL24 CDL23 CDL22 CDL21 CDL20
CDH27 CDH26 CDH25 CDH24 CDH23 CDH22 CDH21 CDH20
CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0
0
0
?
00
16
00
16
HC5 HC4 HC3 HC2 HC1 HC0
CRD7 CRD6 CRD5 CRD4 CRD3
DPS7 DPS6 DPS5 DPS4 DPS3
0
0
?
0
0
1
Bank control register (BK)
A-D conversion register (AD)
A-D control register (ADCON)
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer 4 (T4)
Timer mode register 1 (TM1)
Timer mode register 2 (TM2)
I
2
C
data shift register (S0)
I
2
C
address register (S0D)
I
2
C
status register (S1)
I
2
C
control register (S1D)
I
2
C
clock control register (S2)
CPU mode
register (CM)
Interrupt request
register 1 (IREQ1)
Interrupt request
register 2 (IREQ2)
Interrupt control
register 1 (ICON1)
Interrupt control
register 2 (ICON2)
BK7 BK6
0
0
0
BK3 BK2 BK1 BK0
0
ADVREF
ADSTR
ADIN2 ADIN1 ADIN0
0
?
0
TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10
TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20
D7
D6
D5
D4
D3
D2
D1
D0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
RBW
MST TRX BB
PIN
AL AAS AD0 LRB
10BIT
BSEL1 BSEL0
SAD
ALS ESO BC2 BC1 BC0
ACK FAST
ACK
BIT MODE
CCR4 CCR3 CCR2 CCR1 CCR0
0
0
0
CM7 CM6 CM5
1
1
CM2
0
0
ADR
VSCR
OSDR
TM4R TM3R TM2R TM1R
0
TM56R
IICR IN2R CKR SIOR
DSR
IN1R
CK0
ADE
VSCE
OSDE
TM4E TM3E TM2E TM1E
TM56S TM56E
IICE IN2E CKE SIOE DSE IN1E
00
16
0 ?
00
16
00
16
00
16
00
16
0 0
00
16
00
16
? ?
00
16
09
16
?
00
16
?
0 1
FF
16
07
16
FF
16
07
16
00
16
00
16
?
00
16
1 0
00
16
00
16
3C
16
00
16
00
16
00
16
00
16
?
0
?
0
0
0
?
?
?
0
0
0
0
0
?
Fig. 12.2.4 Memory Map of Special Function Register 1 (SFR2) (2)
Rev. 1.0
16
RENESAS [ RENESAS TECHNOLOGY CORP ]
