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MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12. FUNCTIONAL DESCRIPTION
12.1. CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
12.1.1 CPU Mode Register
The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allo-
cated at address 00FB
16
.
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 1
0 0
CPU mode register (CM) [Address 00FB
16
]
Name
0, 1 Processor mode bits
(CM0, CM1)
B
Functions
b1 b0
After reset
R W
0
R W
0
0
1
1
0: Single-chip mode
1:
0:
Not available
1:
1
1
R W
R W
R W
R W
2 Stack page selection
bit (CM2) (See note)
3, 4 Fix these bits to “1.”
5 X
COUT
drivability
selection bit (CM5)
6 Main Clock (X
IN
–X
OUT
)
stop bit
(CM6)
7 Internal system clock
selection bit
(CM7)
0: 0 page
1: 1 page
0: LOW drive
1: HIGH drive
0: Oscillating
1: Stopped
1
0
0: X
IN
–X
OUT
selected
(high-speed mode)
1: X
CIN
–X
COUT
selected
(low-speed mode)
Note:
This bit is set to “1” after the reset release.
0
R W
Fig. 12.1.1 CPU Mode Register
Rev. 1.0
12
RENESAS [ RENESAS TECHNOLOGY CORP ]
