MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
The vertical position for each block can be set in 1024 steps (where
and values “0016” to “0316” in vertical position register 2i (i = 1 to 12)
(addresses 023016 to 023B16). The structure of the vertical position
registers is shown in Figure 70 and 71.
each step is 1TH (TH: HSYNC cycle)) as values “0016” to “FF16” in
vertical position register 1i (i = 1 to 12) (addresses 022016 to 022B16)
Vertical Position Register 1i
b7 b6 b5b4 b3 b2b1 b0
Vertical position register 1i (VP1i) (i = 1 to 16) [Addresses 022016 to 022F16
]
B
Name
Functions
After reset
R
W
0
to
7
Vertical display start positions
(low-order 8 bits)
TH ✕
(setting value of low-order 2 bits of VP2i
+ setting value of low-order 4 bits of VP1i
+ setting value of low-order 4 bits of VP1i
Indeterminate R W
Control bits of vertical
display start positions
(VP1i0 to VP1i7)
(See note 1)
✕
✕
✕
162
161
160)
Notes 1: Set values except “0016” “0116” to VP1i when VP2i is “00 16.”
2: T is cycle of HSYNC
H
.
Fig. 70. Vertical Position Register 1
Vertical Position Register 2i
b7 b6 b5b4 b3 b2b1 b0
Vertical position register 2i (VP2i) (i = 1 to 16) [Addresses 023016 to 023F16
]
B
Name
Functions
After reset
R
W
0, 1
Vertical display start positions
(high-order 2 bits)
TH ✕
(setting value of low-order 2 bits of VP2i
+ setting value of low-order 4 bits of VP1i
+ setting value of low-order 4 bits of VP1i
Indeterminate R W
Control bits of vertical
display start positions
(VP1i0, VP1i1)
(See note 1)
✕
✕
✕
162
161
160)
2
to
7
Indeterminate R —
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are indeterminate.
Notes 1: Set values except “0016” “0116” to VP1i when VP2i is “00 16.”
2: T is cycle of HSYNC
H
.
Fig. 71. Vertical Position Register 2
71
RENESAS [ RENESAS TECHNOLOGY CORP ]
