MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
OSD Control Register
b7 b6 b5b4 b3 b2b1 b0
OSD control register (OC) [Address 00CE16
]
Functions
After reset
0
R
W
B
Name
0 : All-blocks display off
1 : All-blocks display on
R W
R W
R W
R W
0
1
2
OSD control bit
(OC0) (See note 1)
Scan mode selection 0 : Normal scnan mode
0
0
0
1 : Bi-scan mode
bit (OC1)
Border type selection
bit (OC2)
0 : All bordered
1 : Shadow bordered (See note 2)
Flash mode selection
bit (OC3)
0 : Color signal of character background
part does not flash
3
1 : Color signal of character background
part flashes
4
5
Automatic solid space
control bit (OC4)
0
0
R W
R W
0 : OFF
1 : ON
Window control bit
(OC5)
0 : OFF
1 : ON
b7 b6
6, 7 Layer mixing control
bits (OC6, OC7)
(See note 3)
0
R W
0
0: Logic sum (OR) of layer 1’s
color and layer 2’s color
1: Layer 1’s color has priority
0: Layer 2’s color has priority
1: Do not set.
0
1
1
Notes 1 : Even this bit is switched during display, the display screen
remains unchanged until a rising (falling) of the next V SYNC
.
2 : Shadow border is output at right and bottom side of the font.
3 : Set “00” during displaying extra fonts.
Fig. 64. OSD Control Register
Block Control register i
b7 b6 b5b4 b3 b2b1 b0
Block control register i (BCi) (i=1 to 16) [Addresses 00D016 to 00DF16
](See note 1)
B
Name
Functions
After reset R W
Indeterminate R W
b1 b0
0, 1 Display mode
selection bits
0
0
1
1
0: Display OFF
(BCi0, BCi1)
1: OSD mode
0: CC mode
1: EXOSD mode
2
Border control bit
(BCi2)
0: Border OFF
1: Border ON
Indeterminate R W
Indeterminate R W
b6 b5
b4 b3 CS6 Pre-divide Dot size
ratio
Display
layer
3, 4 Dot size selection
bits (BCi3, BCi4)
0
0
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
1Tc ✕ 1/2H
1Tc ✕ 1H
1.5Tc ✕ 1/2H
1.5Tc ✕ 1H
0
1
0
1
0
0
0
1
—
—
✕ 1
✕ 2
1
0
1
0
0
1
Layer1
1
1
0
1
Indeterminate R W
5, 6 Pre-divide ratio •
layer selection bit
(BCi5, BCi6)
0
0
0
1
1
1
1
0
1
1
—
0
✕ 3
✕ 1
1
1
0
1
—
—
0
1
Layer2
0
0
0
1
✕ 2
1
1
1
0
1
Indeterminate R W
7
OUT2 output control bit BC17: Window top boundary
(BCi7) (See note 2) BC27: Window bottom boundary
Notes 1: Note that MASK version the block control registers at addresses 00D0 16 to 00DB16
when programming.
2: Bit 4 of the color code 1 controls OUT1 output when bit 7 is "0".
Bit 4 of the color code 1 controls OUT2 output when bit 7 is "1".
3: CS6 : Bit 6 of the clock control register (address 0216 16
4: Tc : Pre-devided clock period for OSD
5: H : Hsync
)
Fig. 65. Block Control Registers
67