MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
The display position in the vertical direction is determined by count-
ing the horizontal sync signal (HSYNC). At this time, when VSYNC and
HSYNC are positive polarity (negative polarity), it starts to count the
rising edge (falling edge) of HSYNC signal from after fixed cycle of
rising edge (falling edge) of VSYNC signal. So interval from rising edge
(falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC
signal needs enough time (2 machine cycles or more) for avoiding
jitter. The polarity of HSYNC and VSYNC signals can select with the
I/O polarity control register (address 021716).
8 machine cycles
or more
V
SYNC signal input
control
0.25 to 0.50 [µs]
( at f(XIN) = 8MHz)
siSgYnNaCl in
V
microcomputer
Period of counting
H
SYNC signal
(Note 2)
H
SYNC
signal input
8 machine cycles
or more
1
2
3
4
5
Not count
When bits 0 and 1 of the I/O polarity control register
(address 021716) are set to “1” (negative polarity)
Notes 1 : The vertical position is determined by counting falling edge of
SYNC signal after rising edge of VSYNC control signal in the
H
microcomputer.
2 : Do not generate falling edge of HSYNC signal near rising edge
of VSYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles
or more.
Fig. 69. Supplement Explanation for Display Position
70
RENESAS [ RENESAS TECHNOLOGY CORP ]
