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M37274EFSP 参数 Datasheet PDF下载

M37274EFSP图片预览
型号: M37274EFSP
PDF下载: 下载PDF文件 查看货源
内容描述: 单片8位CMOS单片机结合闭合字幕解码器和屏幕显示控制器 [SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER]
分类和应用: 解码器显示控制器微控制器和处理器外围集成电路光电二极管瞄准线计算机可编程只读存储器时钟
文件页数/大小: 148 页 / 1926 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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MITSUBISHI MICROCOMPUTERS  
M37274EFSP  
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER  
and ON-SCREEN DISPLAY CONTROLLER  
Internal clock : The serial I/O counter is set to “7” during the write  
External clock : The an external clock is selected as the clock source,  
the interrupt request is set to “1” after the transfer clock has been  
counted 8 counts. However, transfer operation does not stop, so the  
clock should be controlled externally. Use the external clock of 500kHz  
or less with a duty cycle of 50%.  
cycle into the serial I/O register (address 021416), and the transfer  
clock goes “H” forcibly. At each falling edge of the transfer clock after  
the write cycle, serial data is output from the SOUT pin. Transfer di-  
rection can be selected by bit 5 of the serial I/O mode register. At  
each rising edge of the transfer clock, data is input from the SIN pin  
and data in the serial I/O register is shifted 1 bit.  
The serial I/O timing is shown in Figure 20. When using an external  
clock for transfer, the external clock must be held at HIGH for initial-  
izing the serial I/O counter. When switching between an internal clock  
and an external clock, do not switch during transfer. Also, be sure to  
initialize the serial I/O counter after switching.  
After the transfer clock has counted 8 times, the serial I/O counter  
becomes “0” and the transfer clock stops at HIGH. At this time the  
interrupt request bit is set to “1.”  
Notes 1: On programming, note that the serial I/O counter is set by  
writing to the serial I/O register with the bit managing in-  
structions, such as SEB and CLB.  
2: When an external clock is used as the synchronous clock,  
write transmit data to the serial I/O register when the trans-  
fer clock input level is HIGH.  
Synchronous clock  
Transfer clock  
Serial I/O register  
write signal  
(Note)  
Serial I/O output  
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D7  
SOUT  
Serial I/O input  
S
IN  
Interrupt request bit is set to “1”  
Note : When an internal clock is selected, the S OUT pin is at high-impedance after transfer is completed.  
Fig. 20. Serial I/O Timing (for LSB first)  
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