MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Notes 1 : 1TC (TC : OSD clock cycle divided by prescaler) gap oc-
2 : The horizontal start position is based on the OSD clock
source cycle selected for each block. Accordingly, when 2
blocks have different OSD clock source cycles, their hori-
zontal display start position will not match.
curs between the horizontal display start position set by
the horizontal position register and the most left dot of the
1st block. Accordingly, when 2 blocks have different pre-
divide ratios, their horizontal display start position will not
match.
HSYNC
1TC
Block 1 (Pre-divide ratio =1, clock source =data slicer clock)
1TC
1TC
4TOSC✕N
Note 1
Note 2
Block 2 (Pre-divide ratio =2, clock source =data slicer clock)
Block 3 (Pre-divide ratio =3, clock source =data slicer clock)
Block 4 (Pre-divide ratio =3, clock source =OSC1)
1TC
4TOSC’✕N
Fig. 57. Notes on horizontal display start position
ter), refer to Figure 59 (the structure of the clock source control reg-
(3) Dot Size
The dot size can be selected by a block unit. The dot size in vertical
direction is determined by dividing HSYNC in the vertical dot size con-
trol circuit. The dot size in horizontal is determined by dividing the
following clock in the horizontal dot size control circuit : the clock
gained by dividing the OSD clock source (data slicer clock, OSC1) in
the pre-divide circuit. The clock cycle divided in the pre-divide circuit
is defined as 1TC.
ister).
The block diagram of dot size control circuit is shown in Figure 58.
Notes 1 : The pre-divide ratio = 3 cannot be used in the CC mode.
2 : The pre-divide ratio of the OSD mode block on the layer 2
must be same as that of the CC mode block on the layer 1
by bit 6 of the clock source control register.
The dot size of the layer 1 is specified by bits 6 to 3 of the block
control register.
3 : In the bi-scan mode, the dot size in the vertical direction is
2 times as compared with the normal mode. Refer to “(13)
Scan Mode” about the scan mode.
The dot size of the layer 2 is specified by the following bits : bits 3
and 4 of the block control register, bit 6 of the clock source control
register. Refer to Figure 50 (the structure of the block control regis-
OSC1
Clock cycle
= 1TC
Synchronization
Horizontal dot size
control circuit
Cycle✕2
Cycle✕3
circuit
CS0
Data slicer clock
Pre-divide circuit
Vertical dot size
control circuit
HSYNC
OSD control circuit
Fig. 58. Block diagram of dot size control circuit
51
RENESAS [ RENESAS TECHNOLOGY CORP ]
