MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
7
0
Block control register i
(i = 1 to 16)
(BCi : addresses 00D016 to 00DF)
0
7
OSD control register
(OC : address 00CE16
)
Display mode selection bits
b1 b0
OSD control bit (Note 1)
0 : All-blocks display off
1 : All-blocks display on
0
0
1
1
0 : Display OFF
1 : OSD mode
0 : CC mode
Scan mode selection bit
0 : Normal scan mode
1 : Bi-scan mode
1 : EXOSD mode
Border control bit
0 : Border OFF
1 : Border ON
Border type selection bit
0 : All bordered
1 : Shadow bordered (Note 2)
Dot size selection bit
Refer to Table 11.
Flash mode selection bit
0 : Color signal of character
background part does not
flash
1 : Color signal of character
background part flashes
Pre-divide ratio
bits
• layer selection
Refer to Table 11.
OUT 2 output control bit (Note)
0 : OUT2 output OFF
1 : OUT2 output ON
Automatic solid space control
bit
0 : OFF
1 : ON
Notes : Bit 4 of the color code 1 controls OUT1 output
when bit 7 is “0.”
Window control bit
0 : OFF
1 : ON
Bit 4 of the color code 1 controls OUT2 output
when bit 7 is “1.”
Layer mixing control bits (Note 3)
b7 b6
0
0 : Logical sum (OR) of
layer 1’s color and
Fig. 50. Structure of block control registers
layer 2’s color
0
1
1
1 : Layer 1’s color has priority
0 : Layer 2’s color has priority
1 : Do not set
Notes 1 : Even this bit is switched during display, the display screen
remains unchanged until a rising (falling) of the next VSYNC
.
2 : Shadow border is output at right and bottom side of the font.
3 : Set “00” during displaying extra fonts.
Table 11. Setting value of block control registers
Pre-divide
ratio
Fig. 49. Structure of OSD control register
b6 b5 b4 b3 CS6
Dot size
Display layer
0
0
0
1
1TC ✕ 1/2H
1TC ✕ 1H
2TC ✕ 2H
3TC ✕ 3H
1TC ✕ 1/2H
1TC ✕ 1H
2TC ✕ 2H
3TC ✕ 3H
1TC ✕ 1/2H
1TC ✕ 1H
2TC ✕ 2H
3TC ✕ 3H
1TC ✕ 1/2H
1TC ✕ 1H
1TC ✕ 1/2H
1TC ✕ 1H
1.5TC ✕ 1/2H
1.5TC ✕ 1H
0
0
0
1
—
—
✕ 1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
Layer 1
✕ 2
1
1
0
0
1
1
1
0
1
1
—
0
✕ 3
✕ 1
✕ 2
1
1
—
—
0
Layer 2
0
1
1
1
Notes 1: CS6 : Bit 6 of clock control register (Address 021616)
2: TC : OSD clock cycle divided in the pre-divide circuit
3: H : HSYNC
47
RENESAS [ RENESAS TECHNOLOGY CORP ]
