MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(5) Field Determination Display
7
0
To display the block with vertical dot size of 1/2H, whether an even
field or an odd field is determined through differences in a synchro-
nizing signal waveform of interlacing system. The dot line 0 or 1 (re-
fer to Figure 62) corresponding to the field is displayed alternately.
In the following, the field determination standard for the case where
both the horizontal sync signal and the vertical sync signal are nega-
tive-polarity inputs will be explained. A field determination is deter-
mined by detecting the time from a falling edge of the horizontal sync
signal until a falling edge of the VSYNC control signal (refer to Figure
54) in the microcomputer and then comparing this time with the time
of the previous field. When the time is longer than the comparing
time, it is regarded as even field. When the time is shorter, it is re-
garded as odd field
I/O polarity control register
(PC : address 021716
)
HSYNC input polarity switch bit
0 : Positive polarity input
1 : Negative polarity input
V
SYNC input polarity switch bit
0 : Positive polarity input
1 : Negative polarity input
R/G/B output polarity switch bit
0 : Positive polarity output
1 : Negative polarity output
The contents of this field can be read out by the field determination
flag (bit 7 of the I/O polarity control register at address 021716). A dot
line is specified by bit 6 of the I/O polarity control register (refer to
Figure 62).
I1, I2 output polarity switch bit
0 : Positive polarity output
1 : Negative polarity output
However, the field determination flag read out from the CPU is fixed
to “0” at even field or “1” at odd field, regardless of bit 6.
OUT1 output polarity switch bit
0 : Positive polarity output
1 : Negative polarity output
OUT2 output polarity switch bit
0 : Positive polarity output
1 : Negative polarity output
Display dot line selection bit (Note)
0 : “
” at even field
” at odd field
” at even field
” at odd field
“
1 : “
“
Field determination flag
0 : Even field
1 : Odd field
Note : Refer to Figure 62.
Fig. 61. Structure of I/O polarity control register
53
RENESAS [ RENESAS TECHNOLOGY CORP ]
