EIT
4.4 EIT Processing Mechanism
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4.4 EIT Processing Mechanism
The EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/
Os. It also has the backup registers for the PC and PSW (the BPC register and the BPSW field of the PSW
register). The EIT processing mechanism is shown below.
M32R/ECU
M32R CPU core
High
RI
RI
RESET#
AE, RIE, FPE, TRAP
Priority
SBI
EI
SBI
EI
SBI#
Interrupt
controller
(ICU)
Internal
peripheral
I/Os
Low
IE flag
(PSW)
BPC register
PC register
BPSW PSW
PSW register
Figure 4.4.1 EIT Processing Mechanism
32180 Group User’s Manual (Rev.1.0)
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