EIT
4.2 EIT Events
4
5) Invalid Operation Exception (IVLD)
The exception occurs when an invalid operation is executed. The following table shows the operation
results and the respective conditions in which each IVLD occurs.
Table 4.2.6 Operation Results When an IVLD Occurred
Operation Result (Content of the Destination Register)
When the IVLD EIT
When the IVLD EIT processing is masked (Note 1) processing is executed
(Note 2)
Occurrence Condition
Operation for SNaN operand
+Infinity-(+Infinity), -Infinity-(-Infinity)
0 x Infinity
QNaN
0 / 0, Infinity / Infinity
When FTOI Return value when pre-conversion signed bit is:
instruction was "0": H7FFF FFFF
No change
When an integer conversion
overflowed
executed
"1": H8000 0000
When NaN or Infinity was converted
into an integer
When FTOS Return value when pre-conversion signed bit is:
instruction was "0": H0000 7FFF
executed
"1": HFFFF 8000
When < or > comparison was performed on NaN
Comparison results (comparison invalid)
Note 1: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "0"
Note 2: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "1"
Note: • NaN (Not a Number)
SNaN (Signaling NaN): a NaN in which the MSB of the decimal fraction is "0". When SNaN is used as the
source operand in an operation, an IVLD occurs. SNaNs are useful in identifying program bugs when used
as the initial value in a variable. However, SNaNs cannot be generated by hardware.
QNaN (Quiet NaN): a NaN in which the MSB of the decimal fraction is "1". Even when QNaN is used as the
source operand in an operation, an IVLD will not occur (excluding comparison and format conversion).
Because a result can be checked by the arithmetic operations, QNaN allows the user to debug without
executing an EIT processing. QNaNs are created by hardware.
6) Unimplemented Exception (UIPL)
The exception occurs when the denormalized number zero flush (DN) bit (FPSR register bit 23) = "0" and
a denormalized number is given as an operation operand. (Note 1)
Because the UIPL has no enable bits available, it cannot be masked when they occur. The destination
register remains unchanged.
Note 1: A UDF occurs when the intermediate result of an operation is a denormalized number, in which case if
the DN bit (FPSR register bit 23) = "0", an UIPL occurs.
4.2.2 Interrupt
(1) Reset Interrupt (RI)
Reset Interrupt (RI) is always accepted by entering the RESET# signal. The reset interrupt is assigned the
highest priority.
For details about the reset interrupt, see Chapter 7, “Reset.”
(2) System Break Interrupt (SBI)
System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault
condition is notified by an external watchdog timer. This interrupt can only be used in cases when after interrupt
processing, control will not return to the program that was being executed when the interrupt occurred.
(3) External Interrupt (EI)
External Interrupt (EI) is requested from internal peripheral I/Os managed by the interrupt controller. The
interrupt controller manages these interrupts by assigning each one of eight priority levels including an
interrupt-disabledstate.
32180 Group User’s Manual (Rev.1.0)
4-5
RENESAS [ RENESAS TECHNOLOGY CORP ]
