EIT
4.2 EIT Events
4
4.2 EIT Events
4.2.1 Exception
(1) Reserved Instruction Exception (RIE)
Reserved Instruction Exception (RIE) occurs when execution of a reserved instruction (unimplemented
instruction) is detected.
(2) Address Exception (AE)
Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store
instructions.
(3) Floating-point Exception (FPE)
Floating-point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions
specified in the IEEE 754 standard (OVF/UDF/IXCT/DIV0/IVLD) is detected. Each exception processing is
outlined below.
1) Overflow Exception (OVF)
The exception occurs when the absolute value of the operation result exceeds the largest describable
precision in the floating-point format. The following table shows the operation results when an OVF oc-
curs.
Table 4.2.1 Operation Results When an OVF Occurred
Operation Result (Content of the Destination Register)
Rounding Mode
Sign of the Result
When the OVF EIT processing is
masked (Note 1)
When the OVF EIT processing is
executed (Note 2)
+
-
+MAX
-Infinity
+Infinity
-MAX
-Infinity
+Infinity
0
+
-
No change
+
-
+MAX
-MAX
+
-
+Infinity
-Infinity
Nearest
Note 1: When the overflow exception enable (EO) bit (FPSR register bit 20) = "0"
Note 2: When the overflow exception enable (EO) bit (FPSR register bit 20) = "1"
Note: • If an OVF occurs while EIT processing for OVF is masked, an IXCT occurs at the same time.
• +MAX = H’7F7F FFFF, –MAX = H’FF7F FFFF
2) Underflow Exception (UDF)
The exception occurs when the absolute value of the operation result is less than the largest describable
precision in the floating-point format. The following table shows the operation results when a UDF occurs.
Table 4.2.2 Operation Results when a UDF Occurred
Operation Result (Content of the Destination Register)
When UDF EIT processing is masked (Note 1)
When UDF EIT processing is executed (Note 2)
No change
DN = 0: An unimplemented exception occurs
DN = 1: 0 is returned
Note 1: When the underflow exception enable (EU) bit (FPSR register bit 18) = "0"
Note 2: When the underflow exception enable (EU) bit (FPSR register bit 18) = "1"
32180 Group User’s Manual (Rev.1.0)
4-3
RENESAS [ RENESAS TECHNOLOGY CORP ]
