ADDRESS SPACE
3.4 Internal RAM and SFR Areas
3
0
7 8
15
0
7 8
15
+0 address +1 address
+0 address +1 address
H'0080 0000
H'0080 078C
MJT(TID0)
Interrupt Controller
(ICU)
H'0080 078E
H'0080 0790
Multijunction
timer (MJT)
MJT(TOU0)
H'0080 007E
H'0080 0080
H'0080 07E2
A-D0 Converter
Serial I/O 0–3
Wait Controller
H'0080 00EE
H'0080 0100
H'0080 0A00
H'0080 0A26
Serial I/O 4–5
H'0080 0146
H'0080 0180
H'0080 0A80
H'0080 0AEE
A-D1 Converter
H'0080 0186
H'0080 01E0
H'0080 0B8C
Flash control
MJT(TID1)
MJT(TOU1)
H'0080 0B8E
H'0080 0B90
H'0080 01F8
H'0080 0200
H'0080 0BE2
MJT (common part)
MJT(TOP)
H'0080 023E
H'0080 0240
H'0080 0C8C
H'0080 02FE
H'0080 0300
MJT(TID2)
MJT(TOU2)
Multijunction
timer (MJT)
H'0080 0C8E
H'0080 0C90
Multijunction
timer (MJT)
MJT(TIO)
H'0080 03BE
H'0080 03C0
H'0080 0CE2
MJT(TMS)
H'0080 03D8
H'0080 03E0
H'0080 0FE0
MJT(TML0)
DMAC
MJT(TML1)
CAN0
H'0080 0FFE
H'0080 1000
H'0080 03FE
H'0080 0400
H'0080 0478
H'0080 11FE
H'0080 0700
H'0080 077F
H'0080 1400
H'0080 15FE
Input/output port
CAN1
Note: • The Real-time Debugger (RTD) is an independent module that is operated from the outside, and is transparent to
the CPU.
Figure 3.4.2 Outline Mapping of the SFR Area
32180 Group User’s Manual (Rev.1.0)
3-7
RENESAS [ RENESAS TECHNOLOGY CORP ]
