ADDRESS SPACE
3.2 Operation Modes
3
3.2 Operation Modes
The microcomputer is placed in one of the following modes depending on how CPU operation mode is set by
MOD0 and MOD1 pins. The operation mode used for rewriting the internal flash memory is described separately
in Section 6.5, “Programming the Internal Flash Memory.”
Table 3.2.1 Operation Mode Settings
MOD0
VSS
MOD1
VSS
Operation mode (Note 2)
Single-chip mode
VSS
VCCE
VSS
External extension mode
Processor mode (FP = VSS)
Reserved (use inhibited)
VCCE
VCCE
VCCE
Note 1: Connect VCCE and VSS to the VCCE input power supply and ground, respectively.
Note 2: For the operation mode used to rewrite the internal flash memory (FP = VCCE) which is not shown in the above
table, see Section 6.5, “Programming the Internal Flash Memory.”
The internal ROM and extended external areas are located differently depending on how operation mode is set.
(All other areas in the address space are located the same way.) The diagram below shows how the internal ROM
and extended external areas are mapped into the address space in each operation mode. (For flash rewrite mode,
see Section 6.5, “Programming the Internal Flash Memory.”)
Non-CS0 area
H'0000 0000
Internal
Internal
ROM area
(1 Mbytes)
ROM area
(1 Mbytes)
H'000F FFFF
H'0010 0000
CS0 area
CS1 area
CS2 area
CS0 area
CS1 area
H'001F FFFF
H'0020 0000
H'003F FFFF
H'0040 0000
CS2 area
H'005F FFFF
H'0060 0000
CS3 area
CS3 area
H'007F FFFF
<External extension mode>
<Single-chip mode>
<Processor mode>
Figure 3.2.1 Internal ROM and Extended External Area Address Mapping of the M32180F8 in Each Operation Mode
32180 Group User’s Manual (Rev.1.0)
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RENESAS [ RENESAS TECHNOLOGY CORP ]
