CPU
2.3 Control Registers
2
2.3.5 Floating-point Status Register: FPSR (CR7)
b0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
b15
FS
0
FX
0
FU
0
FZ
0
FO
0
FV
0
0
0
0
0
0
0
0
0
0
0
b16
0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
b31
DN
1
CE
0
CX
0
CU
0
CZ
0
CO
0
CV
0
RM
EZ
0
EO
0
EV
0
EX
0
EU
0
0
0
0
<After reset: H’0000 0100>
b
0
Bit Name
FS
Function
Reflects the logical sum of FU, FZ, FO and FV.
R
R
W
–
Floating-point Exception Summary Bit
1
2
3
4
5
FX
Set to "1" when an inexact exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
R
R
R
R
R
W
W
W
W
W
Inexact Exception Flag
FU
Set to "1" when an underflow exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
Underflow Exception Flag
FZ
Set to "1" when a zero divide exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
Zero Divide Exception Flag
FO
Set to "1" when an overflow exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
Overflow Exception Flag
FV
Set to "1" when an invalid operation exception occurs (if EIT processing
is unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
Invalid Operation Exception Flag
6–16
17
No function assigned. Fix to "0".
0
0
EX
0: Mask EIT processing to be executed when an inexact exception occurs.
1: Execute EIT processing when an inexact exception occurs.
R
W
Inexact Exception Enable Bit
18
19
20
21
EU
0: Mask EIT processing to be executed when an underflow exception
occurs.
R
R
R
R
W
W
W
W
Underflow Exception Enable Bit
1: Execute EIT processing when an underflow exception occurs.
EZ
0: Mask EIT processing to be executed when a zero divide exception
occurs.
Zero Divide Exception Enable Bit
1: Execute EIT processing when a zero divide exception occurs.
EO
0: Mask EIT processing to be executed when an overflow exception
occurs.
Overflow Exception Enable Bit
1: Execute EIT processing when an overflow exception occurs.
EV
0: Mask EIT processing to be executed when an invalid operation
exception occurs.
Invalid Operation Exception Enable Bit
1: Execute EIT processing when an invalid operation exception occurs.
22
23
No function assigned. Fix to "0".
DN
0
0
0: Handle the denormalized number as a denormalized number.
R
W
Denormalized Number Zero Flush Bit 1: Handle the denormalized number as zero.
(Note 2)
24
25
CE
0: No unimplemented operation exception occurred.
R (Note 3)
R (Note 3)
Unimplemented Operation
Exception Cause Bit
1: An unimplemented operation exception occurred. When the bit is
set to "1", the execution of an FPU operation instruction will clear it to "0".
CX
0: No inexact exception occurred.
Inexact Exception Cause Bit
1: An inexact exception occurred. When the bit is set to "1",
the execution of an FPU operation instruction will clear it to "0".
32180 Group User’s Manual (Rev.1.0)
2-5
RENESAS [ RENESAS TECHNOLOGY CORP ]
