CPU
2.3 Control Registers
2
2.3.1 Processor Status Word Register: PSW (CR0)
b0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
b15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
b31
BC
?
SM
0
IE
0
C
0
BSM BIE
?
?
0
0
0
0
0
0
0
0
0
0
BPSW field
PSW field
<After reset: B’0000 0000 0000 0000 ??00 000? 0000 0000>
b
Bit Name
Function
R
0
W
0
0–15
16
No function assigned. Fix to "0".
BSM
Saves value of SM bit when EIT occurs
Saves value of IE bit when EIT occurs
R
W
Backup SM Bit
17
BIE
R
W
Backup IE Bit
18–22
23
No function assigned. Fix to "0".
0
0
BC
Saves value of C bit when EIT occurs
R
W
Backup C Bit
24
25
SM
0: Uses R15 as the interrupt stack pointer
1: Uses R15 as the user stack pointer
R
R
W
W
Stack Mode Bit
IE
0: Does not accept interrupt
1: Accepts interrupt
Interrupt Enable Bit
26–30
31
No function assigned. Fix to "0".
0
0
C
Indicates carry, borrow or overflow resulting
from operations (instruction dependent)
R
W
Condition Bit
The Processor Status Word Register (PSW) indicates the M32R-FPU status. It consists of the current PSW field
which is regularly used, and the BPSW field where a copy of the PSW field is saved when EIT occurs.
The PSW field consists of the Stack Mode (SM) bit, the Interrupt Enable (IE) bit and the Condition (C) bit.
The BPSW field consists of the Backup Stack Mode (BSM) bit, the Backup Interrupt Enable (BIE) bit and the
Backup Condition (BC) bit.
After reset, BSM, BIE and BC are undefined. All other bits are "0".
32180 Group User’s Manual (Rev.1.0)
2-3
RENESAS [ RENESAS TECHNOLOGY CORP ]
