MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
10
10.3.3 TOP Related Register Map
Shown below is a TOP related register map.
TOP Related Register Map (1/2)
Address
+0 address
+1 address
See pages
10-75
b0
b7 b8
TOP0 Counter
(TOP0CT)
b15
H'0080 0240
H'0080 0242
H'0080 0244
TOP0 Reload Register
(TOP0RL)
(Use inhibited area)
10-76
H'0080 0246
TOP0 Correction Register
(TOP0CC)
10-77
|
(Use inhibited area)
H'0080 0250
H'0080 0252
H'0080 0254
TOP1 Counter
(TOP1CT)
10-75
10-76
TOP1 Reload Register
(TOP1RL)
(Use inhibited area)
H'0080 0256
TOP1 Correction Register
(TOP1CC)
10-77
|
(Use inhibited area)
H'0080 0260
H'0080 0262
H'0080 0264
H'0080 0266
|
TOP2 Counter
(TOP2CT)
TOP2 Reload Register
(TOP2RL)
10-75
10-76
(Use inhibited area)
TOP2 Correction Register
(TOP2CC)
10-77
(Use inhibited area)
H'0080 0270
H'0080 0272
H'0080 0274
H'0080 0276
|
TOP3 Counter
(TOP3CT)
TOP3 Reload Register
(TOP3RL)
10-75
10-76
(Use inhibited area)
TOP3 Correction Register
(TOP3CC)
(Use inhibited area)
10-77
H'0080 0280
H'0080 0282
H'0080 0284
H'0080 0286
|
TOP4 Counter
(TOP4CT)
TOP4 Reload Register
(TOP4RL)
10-75
10-76
(Use inhibited area)
TOP4 Correction Register
(TOP4CC)
(Use inhibited area)
10-77
H'0080 0290
H'0080 0292
H'0080 0294
H'0080 0296
H'0080 0298
TOP5 Counter
(TOP5CT)
TOP5 Reload Register
(TOP5RL)
10-75
10-76
(Use inhibited area)
TOP5 Correction Register
(TOP5CC)
(Use inhibited area)
10-77
32180 Group User’s Manual (Rev.1.0)
10-68