MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
10
<Count clock-dependent delay>
• Because the timer operates synchronously with the count clock, there is a count clock-dependent delay
from when the timer is enabled till when it actually starts operating. In operation mode where the F/F output
is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is
inverted.
Write to the enable bit
BCLK
Count clock period
Count clock
Enable
Count clock-dependent
delay
F/F operation (Note 1)
Inverted
Note 1: This applies to the case where F/F output is inverted when the timer is enabled.
Figure 10.3.2 Count Clock Dependent Delay
32180 Group User’s Manual (Rev.1.0)
10-67
RENESAS [ RENESAS TECHNOLOGY CORP ]
