M32C/83 Group (M32C/83, M32C/83T)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers.
A register bank comprises 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) out of 28 CPU registers. Two
sets of register banks are provided.
b31
b15
b0
General Register
R2
R3
R0H
R1H
R0L
R1L
Data Register(1)
R2
R3
b23
A0
A1
SB
FB
Address Register(1)
Static Base Register(1)
Frame Base Register(1)
USP
ISP
User Stack Pointer
Interrupt Stack Pointer
Interrupt Table Register
Program Counter
INTB
PC
FLG
Flag Register
b15
b8 b7
U
b0
IPL
I
O B S Z D C
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Space
Processor Interrupt Priority Level
Reserved space
b15
b0
High-Speed Interrupt Register
DMAC Associated Register
SVF
Flag Save Register
PC Save Register
Vector Register
b23
SVP
VCT
b7
b0
DMD0
DMD1
DMA Mode Register
b15
DCT0
DCT1
DRC0
DRC1
DMA Transfer Count Register
DMA Transfer Count Reload Register
DMA Memory Address Register
DMA Memory Address Reload Register
DMA SFR Address Register
b23
DMA0
DMA1
DRA0
DRA1
DSA0
DSA1
NOTES:
1. A register bank comprises these registers. Two sets of register banks are provided.
Figure 2.1 CPU Register
Page 18
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
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