M32C/83 Group (M32C/83, M32C/83T)
3. Memory
Figure 3.1 shows a memory map of the M32C/83 group (M32C/83, M32C/83T).
M32C/83 group (M32C/83, M32C/83T) provides 16-Mbyte address space from addresses 00000016 to
FFFFFF16.
The internal ROM is allocated lower addresses beginning with address FFFFFF16. For example, a 64-
Kbyte internal ROM is allocated addresses FF000016 to FFFFFF16.
The fixed interrupt vectors are allocated addresses FFFFDC16 to FFFFFF16. It stores the starting address
of each interrupt routine. Refer to 10. Interrupts for details.
The internal RAM is allocated higher addresses beginning with address 00040016. For example, a 10-
Kbyte internal RAM is allocated addresses 00040016 to 002BFF16. Besides storing data, it becomes stacks
when the subroutine is called or an interrupt is acknowledged.
SFR, consisting of control registers for peripheral functions such as I/O port, A/D conversion, serial I/O, and
timers, is allocated addresses 00000016 to 0003FF16. All addresses, which have nothing allocated within
SFR, are reserved space and cannot be accessed by users.
The special page vectors are allocated addresses FFFE0016 to FFFFDB16. It is used for the JMPS instruc-
tion and JSRS instruction. Refer to the Renesas publication Software Manual for details.
In memory expansion mode and microprocessor mode, some space are reserved and cannot be accessed
by users.
00000016
SFR
00040016
Internal RAM
007FFF16
FFFE0016
FFFFDC16
Reserved Space
00800016
Special Page
Vector Table
External Space(1)
Undefined Instruction
Overflow
BRK Instruction
Address Match
F0000016
F8000016
Reserved Space(2)
Internal ROM(3)
Watchdog Timer(4)
NMI
Reset
FFFFFF16
FFFFFF16
NOTES:
1. In memory expansion and microprocessor modes
2. In memory expansion mode. This space becomes external space in microprocessor mode.
3. This space can be used in single-chip mode and memory expansion mode. This space becomes external
space in microprocessor mode.
4. Watchdog timer interrupt, oscillation stop detection interrupt, and low voltage detection interrupt share vectors.
Figure 3.1 Memory Map
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