M32C/83 Group (M32C/83, M32C/83T)
1.6 Pin Description
Table 1.6 Pin Description (100-Pin and 144-Pin Packages)
Classsfication
Symbol
I/O Type
I
Function
Apply 3.0 to 5.5V to both VCC pin.
Apply 0V to the VSS pin. (1)
Power Supply VCC
VSS
Analog Power AVCC
I
Supplies power to the A/D converter. Connect the AVCC pin to VCC and the
Supply
AVSS
AVSS pin to VSS
____________
___________
Reset Input
CNVSS
RESET
CNVSS
I
I
The microcomputer is in a reset state when "L" is applied to the RESET pin
Switches processor mode. Connect the CNVSS pin to VSS to start up in single-
chip mode or to VCC to start up in microprocessor mode
Switches data bus width in external memory space 3. The data bus is 16
bits wide when the BYTE pin is held "L" and 8 bits wide when it is held "H".
Set to either. Connect the BYTE pin to VSS to use the microcomputer in
single-chip mode
Input to Switch BYTE
External Data Bus
Width(2)
I
Bus Control
Pins(2)
D0 to D7
I/O
I/O
Inputs and outputs data (D0 to D7) while accessing an external memory
space with separate bus
D8 to D15
Inputs and outputs data (D8 to D15) while accessing an external memory
space with 16-bit separate bus
A0 to A22
O
O
Outputs address bits A0 to A22
______
A23
Outputs inversed address bit A23
A0/D0 to
A7/D7
I/O
Inputs and outputs data (D0 to D7) and outputs 8 low-order address bits (A0
to A7) by time-sharing while accessing an external memory space with
multiplexed bus
A8/D8 to
A15/D15
I/O
Inputs and outputs data (D8 to D15) and outputs 8 middle-order address bits
(A8 to A15) by time-sharing while accessing an external memory space with
16-bit multiplexed bus
_______
_______
______
______
Outputs CS0 to CS3 that are chip-select signals specifying an external space
CS0 to CS3
O
O
_________
______
________ _________
______ ________
_____
________
________
WRH can be
/ WR
WRL
Outputs WRL, WRH, (WR, BHE) and RD signals. WRL and
______
_______
_________
WRH / _B__H___E__
switched with WR and BHE by program
________
_____
WRL, _W___R___H__ and RD selected:
_____
RD
If external data bus is 16 bits wide, data is written to an even address in
________
external memory space when WRL is held "L".
Data is written to an odd address when _W___R___H__ is held "L".
_____
Data is read when RD is held "L".
______
_____
WR, _B__H___E__ and RD selected:
______
Data is written to external memory space when WR is held "L".
_____
Data in an external memory space is read when RD is held "L".
An odd address is accessed when _B__H___E__ is held "L".
_____
Select _W___R__, _B__H___E__ and RD for external 8-bit data bus.
ALE is a signal latching the address
ALE
O
I
The microcomputer is placed in a hold state while the _H__O___L__D__ pin is held "L"
Outputs an "L" signal while the microcomputer is placed in a hold state
Bus is placed in a wait state while the _R__D___Y__ pin is held "L"
When DRAM area is accessed, outputs column and row addresses by time-sharing.
__________
HOLD
__________
HLDA
O
I
________
RDY
DRAM Bus
MA
0
to MA12
O
O
______
__________
The DW signal becomes "L" when data is written to the DRAM area. _C__A___S__L__ and CASH are
______
(2)
Control Pin
DW
signals indicating the timing to latch column addresses. The _C__A___S__L__ signal becomes "L" when
__________
CASL
__________
__________
an even address is accessed. The CASH signal becomes "L" when an odd address is
accessed. _R__A___S__ is a signal latching row addresses.
CASH
________
RAS
I : Input
O : Output
I/O : Input and output
NOTES:
1. Apply 4.2 to 5.5V to the VCC pin when using M32C/83T.
2. Bus control pins in M32C/83T cannot be used.
Page 14
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
RENESAS [ RENESAS TECHNOLOGY CORP ]
