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M3062LFGPFP 参数 Datasheet PDF下载

M3062LFGPFP图片预览
型号: M3062LFGPFP
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片16位CMOS微机 [SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER]
分类和应用: 微控制器和处理器外围集成电路计算机时钟
文件页数/大小: 101 页 / 1125 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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M16C/62P Group (M16C/62P, M16C/62PT)  
5. Electrical Characteristics  
VCC1=VCC2=3V  
Timing Requirements  
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = 20 to 85°C / 40 to 85°C unless otherwise specified)  
(1)  
Table 5.32  
External Clock Input (XIN input)  
Standard  
Symbol  
Parameter  
Unit  
Min.  
Max.  
tc  
External Clock Input Cycle Time  
External Clock Input HIGH Pulse Width  
External Clock Input LOW Pulse Width  
External Clock Rise Time  
(NOTE 2)  
(NOTE 3)  
(NOTE 3)  
ns  
ns  
ns  
ns  
ns  
tw(H)  
tw(L)  
tr  
(NOTE 4)  
(NOTE 4)  
tf  
External Clock Fall Time  
NOTES:  
1. The condition is VCC1=VCC2=2.7 to 3.0V.  
2. Calculated according to the VCC1 voltage as follows:  
106  
--------------------------------------- [ns]  
20 × VCC2 44  
3. Calculated according to the VCC1 voltage as follows:  
106  
20 × VCC1 44  
---------------------------------------  
× 0.4 [ns]  
4. Calculated according to the VCC1 voltage as follows:  
10 × VCC1 + 45 [ns]  
Table 5.33  
Memory Expansion Mode and Microprocessor Mode  
Standard  
Symbol  
Parameter  
Unit  
Min.  
Max.  
tac1(RD-DB)  
tac2(RD-DB)  
tac3(RD-DB)  
tsu(DB-RD)  
Data Input Access Time (for setting with no wait)  
Data Input Access Time (for setting with wait)  
Data Input Access Time (when accessing multiplex bus area)  
Data Input Setup Time  
(NOTE 1)  
(NOTE 2)  
(NOTE 3)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
50  
40  
50  
0
tsu(RDY-BCLK)  
RDY Input Setup Time  
tsu(HOLD-BCLK) HOLD Input Setup Time  
th(RD-DB)  
Data Input Hold Time  
RDY Input Hold Time  
th(BCLK-RDY)  
0
th(BCLK-HOLD) HOLD Input Hold Time  
0
NOTES:  
1. Calculated according to the BCLK frequency as follows:  
9
0.5x10  
----------------------- 60[ns]  
f(BCLK)  
2. Calculated according to the BCLK frequency as follows:  
9
(n 0.5)x10  
f(BCLK)  
------------------------------------ 60 [n s ]  
n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.  
3. Calculated according to the BCLK frequency as follows:  
9
(n 0.5)x10  
f(BCLK)  
------------------------------------ 60 [n s ]  
n is “2” for 2-wait setting, “3” for 3-wait setting.  
Rev.2.41 Jan 10, 2006 Page 67 of 96  
REJ03B0001-0241  
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