M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplex bus selection)
Read timing
BCLK
th(BCLK-CS)
td(BCLK-CS)
th(RD-CS)
4ns.min
tcyc
(0.5×tcyc-10)ns.min
25ns.max
CSi
td(AD-ALE)
th(ALE-AD)
(0.5×tcyc-25)ns.min
(0.5×tcyc-15)ns.min
ADi
/DBi
Address
Data input
Address
tdZ(RD-AD)
8ns.max
th(RD-DB)
0ns.min
tsu(DB-RD)
40ns.min
tac3(RD-DB)
(1.5×tcyc-45)ns.max
td(AD-RD)
0ns.min
th(BCLK-AD)
td(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
th(BCLK-ALE)
25ns.max
−4ns.min
(0.5×tcyc-10)ns.min
ALE
RD
td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
Write timing
BCLK
th(BCLK-CS)
4ns.min
th(WR-CS)
(0.5×tcyc-10)ns.min
tcyc
td(BCLK-CS)
25ns.max
CSi
th(BCLK-DB)
4ns.min
td(BCLK-DB)
40ns.max
ADi
/DBi
Address
Data output
Address
td(DB-WR)
th(WR-DB)
(0.5×tcyc-10)ns.min
td(AD-ALE)
(0.5×tcyc-25)ns.min
(1.5×tcyc-40)ns.min
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
25ns.max
td(AD-WR)
0ns.min
th(BCLK-ALE)
th(WR-AD)
(0.5×tcyc-10)ns.min
−4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR,WRL,
WRH
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : VIL=0.8V, VIH=2.0V
· Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 5.10
Timing Diagram (8)
Rev.2.41 Jan 10, 2006 Page 63 of 96
REJ03B0001-0241
RENESAS [ RENESAS TECHNOLOGY CORP ]
