1. Overview
M16C/62 Group (M16C/62P, M16C/62PT)
PIN CONFIGURATION (top view)
56 55 54 53 52 51
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
P1_2/D10
P1_1/D9
P1_0/D8
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
76
77
78
79
P4_2/A18
P4_3/A19
P4_4/CS0
P4_5/CS1
P4_6/CS2
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
80
81
P4_7/CS3
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
M16C/62 Group
(M16C/62P, M16C/62PT)
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT
AVCC
P9_7/ADTRG/SIN4
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
(1)
(1)
P7_1/RXD2/SCL2/TA0IN/TB5IN
P7_2/CLK2/TA1OUT/V
26
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Package: 100P6Q-A
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
Figure 1.7 Pin Configuration (Top View)
page 14
Rev.2.10 Nov. 07, 2003
of 84