Hardware Protection: Suspends or disables the programming and erasing of flash memory, and
resets the flash memory control register (FLMCR) and erase block registers (EBR1 and EBR2).
Details of hardware protection are as follows.
Function
Protection
Description
Program Erase
Verify*1
Programing When 12 V is not applied to the FVPP pin,
voltage (VPP) FLMCR, EBR1, and EBR2 are initialized,
Disabled
Disabled*2 Disabled
protect
disabling programming and erasing. To obtain
this protection, VPP should not exceed VCC.*3
Reset and
standby
protect
When a reset occurs (including a watchdog
timer reset) or standby mode is entered,
Disabled
Disabled*2 Disabled
FLMCR, EBR1, and EBR2 are initialized,
disabling programming and erasing. Note that
RES input does not ensure a reset unless the
RES pin is held low for at least 20 ms at power-
up (to enable the oscillator to settle), or at least
ten system clock cycles (10ø) during operation.
Interrupt
protect
To prevent damage to the flash memory, if
interrupt input occurs while flash memory is
being programmed or erased, programming or
erasing is aborted immediately. The settings in
FLMCR, EBR1, and EBR2 are retained. This
type of protection can be cleared only by a
reset.
Disabled
Disabled*2 Enabled
Notes: *1 Three modes: program-verify, erase-verify, and prewrite-verify.
*2 All blocks are erase-disabled. It is not possible to specify individual blocks.
*3 For details, see section 19.7, Flash Memory Programming and Erasing Precautions.
19.4.9
Interrupt Handling during Flash Memory Programming and Erasing
If an interrupt occurs*1 while flash memory is being programmed or erased (while the P or E bit of
FLMCR is set), the following operating states can occur.
•
If an interrupt is generated during programming or erasing, programming or erasing is aborted
to protect the flash memory. Since memory cell values after a forced interrupt are
indeterminate, the system will not operate correctly after such an interrut.
•
Program runaway may result because the vector table could not be read correctly in interrupt
exception handling during programming or erasure*2.
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RENESAS [ RENESAS TECHNOLOGY CORP ]
