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HD64F3337YF16 参数 Datasheet PDF下载

HD64F3337YF16图片预览
型号: HD64F3337YF16
PDF下载: 下载PDF文件 查看货源
内容描述: 单片机 [Single-Chip Microcomputer]
分类和应用: 微控制器和处理器外围集成电路
文件页数/大小: 747 页 / 2993 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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15.5  
Interrupts  
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt  
request can be enabled or disabled by the ADIE bit in ADCSR.  
15.6  
Useage Notes  
When using the A/D converter, note the following points:  
15.6.1 Setting Ranges of Analog Power Supply Pins, Etc.  
Analog Input Voltage Range: The voltage applied to analog input pins ANn during A/D  
conversion should be in the range AVSS ANn AVCC (n = 0 to 7).  
AVCC and AVSS Input Voltages: For the AVCC input voltage, set AVSS = VSS. When the A/D  
converter is not used, set AVCC = VCC and AVSS = VSS.  
15.6.2  
Notes on Board Design  
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,  
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close  
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation  
of the analog circuitry due to inductance, adversely affecting A/D conversion values.  
Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog  
reference voltage (AVref), and analog power supply (AVCC) by the analog ground (AVSS). The  
analog ground (AVSS) should be connected to a stable digital ground (VSS) at one point on the  
board.  
15.6.3  
Notes on Noise  
A protection circuit should be connected between AVCC and AVSS as shown in figure 15.7 to  
prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins  
(AN0 to AN7).  
Also, the bypass capacitors connected to AVCC and AVref and the filter capacitors connected to  
AN0 to AN7 must be connected to AVSS.  
If filter capacitors are connected as shown in figure 15.7, the input currents at the analog input  
pins (AN0 to AN7) will be smoothed, which may give rise to error. Error can also occur if A/D  
conversion is frequently performed in scan mode so that the current that charges and discharges  
the capacitor in the sample-and-hold circuit of the A/D converter becomes greater than that input  
348  
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