0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5
Basic
clock
–7.5 pulses
+7.5 pulses
Receive
data
D0
D1
Start bit
Sync
sampling
Data
sampling
Figure 12.18 Sampling Timing (Asynchronous Mode)
M = {(0.5 – 1/2N) – (D – 0.5)/N – (L – 0.5)F} × 100 [%] ................................... (1)
M: Receive margin
N: Ratio of basic clock to bit rate (N=16)
D: Duty factor of clock—ratio of high pulse width to low width (0.5 to 1.0)
L: Frame length (9 to 12)
F: Absolute clock frequency deviation
When D = 0.5 and F = 0
M = (0.5 –1/2 × 16) × 100 [%] = 46.875% ......................................................... (2)
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RENESAS [ RENESAS TECHNOLOGY CORP ]
