•
Four interrupts
TDR-empty, TSR-empty, receive-end, and receive-error interrupts are requested
independently.
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of one serial communication interface channel.
Internal
data bus
Module data bus
RDR
RSR
TDR
TSR
SSR
SCR
SMR
BRR
Internal
clock
ø
øP/4
øP/16
øP/64
Baud rate
generator
RxD
TxD
Communi-
cation
control
Parity
generate
Clock
Parity check
External clock source
SCK
TEI
TXI
RXI
ERI
Interrupt signals
RSR: Receive shift register (8 bits)
RDR: Receive data register (8 bits)
TSR: Transmit shift register (8 bits)
TDR: Transmit data register (8 bits)
SMR: Serial mode register (8 bits)
SCR: Serial control register (8 bits)
SSR: Serial status register (8 bits)
BRR: Bit rate register (8 bits)
Figure 12.1 Block Diagram of Serial Communication Interface
234
RENESAS [ RENESAS TECHNOLOGY CORP ]
