11.1.2
Block Diagram
Figure 11.1 is a block diagram of the watchdog timer.
Internal reset or
internal NMI
(Watchdog timer mode)
Internal
data bus
Overflow
WOVF interrupt
Interrupt
TCNT
TCSR
request signal
Read/write
control
control
(Interval timer mode)
Internal clock source
øP/2
øP/32
Clock
øP/64
Clock
select
øP/128
øP/256
øP/512
øP/2048
øP/4096
TCNT: Timer counter
TCSR: Timer control/status register
Figure 11.1 Block Diagram of Watchdog Timer
Register Configuration
11.1.3
Table 11.1 lists information on the watchdog timer registers.
Table 11.1 Register Configuration
Addresses
Initial
Value
Name
Abbreviation
TCSR
R/W
Write
Read
Timer control/status register
Timer counter
R/(W)*
R/W
H'10
H'00
H'FFA8
H'FFA8
H'FFA8
H'FFA9
TCNT
Note: * Software can write a 0 to clear the status flag bits, but cannot write 1.
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RENESAS [ RENESAS TECHNOLOGY CORP ]
