Figure 4.8 shows an example in which the OCIAE bit is cleared to 0.
CPU write
cycle to TIER
OCIA exception handling
ø
TIER address
Internal address bus
Internal write signal
OCIAE
OCFA
OCIA interrupt signal
Figure 4.8 Contention between Interrupt and Disabling Instruction
The above contention does not occur if the enable bit or flag is cleared to 0 while the interrupt
mask bit (I) is set to 1.
4.4
Note on Stack Handling
In word access, the least significant bit of the address is always assumed to be 0. The stack is
always accessed by word access. Care should be taken to keep an even value in the stack pointer
(general register R7). Use the PUSH Rn and POP Rn (or MOV.W Rn, @–SP and MOV.W @SP+,
Rn) instructions to push and pop registers on the stack.
Setting the stack pointer to an odd value can cause programs to crash. Figure 4.9 shows an
example of damage caused when the stack pointer contains an odd address.
87
RENESAS [ RENESAS TECHNOLOGY CORP ]
