Interrupt
accepted
Instruction prefetch
(first instruction of
interrupt-handling
routine)
Interrupt priority
decision. Wait for
end of instruction.
Vector
fetch
Instruction Internal
prefetch
Internal
process-
ing
process-
ing
Stack
Interrupt request
signal
ø
Internal address
bus
(8)
(1)
(3)
(5)
(6)
(9)
Internal read
signal
Internal write
signal
Internal 16-bit
data bus
(2)
(4)
(1)
(7)
(9)
(10)
(1)
Instruction prefetch address (Pushed on stack. Instruction is executed on return from interrupt-handling
routine.)
(2) (4) Instruction code (Not executed)
(3)
(5)
(6)
(7)
(8)
(9)
(10)
Instruction prefetch address (Not executed)
SP–2
SP–4
CCR
Address of vector table entry
Vector table entry (address of first instruction of interrupt-handling routine)
First instruction of interrupt-handling routine
Figure 4.7 Timing of Interrupt Sequence
85
RENESAS [ RENESAS TECHNOLOGY CORP ]
