4.3.5
Interrupt Handling
Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt
requests, commands the CPU to start the hardware interrupt exception-handling sequence, and
furnishes the necessary vector number. Figure 4.4 shows a block diagram of the interrupt
controller.
Interrupt
CPU
controller
NMI interrupt
*
IRQ0 flag
IRQ0E
Interrupt request
IRQ0
interrupt
Priority
decision
Vector number
IRIC
IEIC
IICI
interrupt
I (CCR)
Note: * For edge-sensed interrupts, these AND gates change to the circuit shown below.
IRQ0 flag
IRQ0 edge
IRQ0E
S
Q
IRQ0 interrupt
Figure 4.4 Block Diagram of Interrupt Controller
The IRQ interrupts and interrupts from the on-chip supporting modules (except for reset selected
for a watchdog timer overflow) all have corresponding enable bits. When the enable bit is cleared
to 0, the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored. These
interrupts can also all be masked by setting the CPU’s interrupt mask bit (I) to 1. Accordingly,
these interrupts are accepted only when their enable bit is set to 1 and the I bit is cleared to 0.
The nonmaskable interrupt (NMI) is always accepted, except in the reset state and hardware
standby mode.
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RENESAS [ RENESAS TECHNOLOGY CORP ]
