HD64F7047 参数 Datasheet PDF下载

Contents

Section 1 Overview............................................................................................1

1.1

1.2

1.3

1.4

Features............................................................................................................................. 2

Internal Block Diagram..................................................................................................... 4

Pin Arrangement ............................................................................................................... 5

Pin Functions .................................................................................................................... 6

Section 2 CPU....................................................................................................13

2.1

2.2

Features............................................................................................................................. 13

Register Configuration...................................................................................................... 14

2.2.1 General Registers (Rn)......................................................................................... 14

2.2.2 Control Registers ................................................................................................. 16

2.2.3 System Registers.................................................................................................. 17

2.2.4 Initial Values of Registers.................................................................................... 17

Data Formats..................................................................................................................... 18

2.3.1 Data Format in Registers ..................................................................................... 18

2.3.2 Data Formats in Memory ..................................................................................... 18

2.3.3 Immediate Data Format ....................................................................................... 19

Instruction Features........................................................................................................... 20

2.4.1 RISC-Type Instruction Set................................................................................... 20

2.4.2 Addressing Modes ............................................................................................... 23

2.4.3 Instruction Format................................................................................................ 26

Instruction Set ................................................................................................................... 29

2.5.1 Instruction Set by Classification .......................................................................... 29

Processing States............................................................................................................... 42

2.6.1 State Transitions .................................................................................................. 42

2.3

2.4

2.5

2.6

Section 3 MCU Operating Modes .....................................................................45

3.1

3.2

3.3

Selection of Operating Modes........................................................................................... 45

Input/Output Pins .............................................................................................................. 46

Explanation of Operating Modes ...................................................................................... 47

3.3.1 Mode 0 (MCU extension mode 0) ....................................................................... 47

3.3.2 Mode 1 (MCU extension mode 1) ....................................................................... 47

3.3.3 Mode 2 (MCU extension mode 2) ....................................................................... 47

3.3.4 Mode 3 (Single chip mode).................................................................................. 47

3.3.5 Clock Mode ......................................................................................................... 47

Address Map ..................................................................................................................... 48

Initial State of This LSI..................................................................................................... 50

3.4

3.5

Rev. 2.00, 09/04, page ix of xl