Section 8 Data Transfer Controller (DTC)........................................................ 109
8.1
8.2
Features............................................................................................................................. 109
Register Descriptions........................................................................................................ 111
8.2.1 DTC Mode Register (DTMR).............................................................................. 112
8.2.2 DTC Source Address Register (DTSAR) ............................................................ 114
8.2.3 DTC Destination Address Register (DTDAR) .................................................... 114
8.2.4 DTC Initial Address Register (DTIAR)............................................................... 114
8.2.5 DTC Transfer Count Register A (DTCRA)......................................................... 114
8.2.6 DTC Transfer Count Register B (DTCRB) ......................................................... 114
8.2.7 DTC Enable Registers (DTER) ........................................................................... 115
8.2.8 DTC Control/Status Register (DTCSR)............................................................... 116
8.2.9 DTC Information Base Register (DTBR) ............................................................ 117
Operation .......................................................................................................................... 118
8.3.1 Activation Sources............................................................................................... 118
8.3.2 Location of Register Information and DTC Vector Table ................................... 118
8.3.3 DTC Operation .................................................................................................... 121
8.3.4 Interrupt Source ................................................................................................... 127
8.3.5 Operation Timing................................................................................................. 127
8.3.6 DTC Execution State Counts ............................................................................... 128
Procedures for Using DTC................................................................................................ 129
8.4.1 Activation by Interrupt......................................................................................... 129
8.4.2 Activation by Software ........................................................................................ 129
8.4.3 DTC Use Example............................................................................................... 130
Cautions on Use ................................................................................................................ 131
8.5.1 Prohibition against DTC Register Access by DTC.............................................. 131
8.5.2 Module Standby Mode Setting ............................................................................ 131
8.5.3 On-Chip RAM ..................................................................................................... 131
8.3
8.4
8.5
Section 9 Bus State Controller (BSC) ............................................................... 133
9.1
9.2
9.3
9.4
9.5
Features............................................................................................................................. 133
Input/Output Pin ............................................................................................................... 135
Register Configuration...................................................................................................... 135
Address Map ..................................................................................................................... 136
Description of Registers.................................................................................................... 138
9.5.1 Bus Control Register 1 (BCR1) ........................................................................... 138
9.5.2 Bus Control Register 2 (BCR2) ........................................................................... 139
9.5.3 Wait Control Register 1 (WCR1) ........................................................................ 140
9.5.4 RAM Emulation Register (RAMER)................................................................... 140
Accessing External Space ................................................................................................. 141
9.6.1 Basic Timing........................................................................................................ 141
9.6.2 Wait State Control ............................................................................................... 142
9.6.3
CS
Assert Period Extension................................................................................. 144
Waits between Access Cycles........................................................................................... 145
9.6
9.7
Rev. 2.00, 09/04, page xii of xl
RENESAS [ RENESAS TECHNOLOGY CORP ]
