Appendix
Appendix A Instruction Set
A.1
Instruction List
Condition Code
Symbol
Rd
Description
General destination register
Rs
General source register
General register
Rn
ERd
ERs
ERn
(EAd)
(EAs)
PC
General destination register (address register or 32-bit register)
General source register (address register or 32-bit register)
General register (32-bit register)
Destination operand
Source operand
Program counter
SP
Stack pointer
CCR
N
Condition-code register
N (negative) flag in CCR
Z (zero) flag in CCR
Z
V
V (overflow) flag in CCR
C (carry) flag in CCR
C
disp
→
Displacement
Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
+
Addition of the operands on both sides
–
Subtraction of the operand on the right from the operand on the left
Multiplication of the operands on both sides
Division of the operand on the left by the operand on the right
Logical AND of the operands on both sides
Logical OR of the operands on both sides
Logical exclusive OR of the operands on both sides
NOT (logical complement)
×
÷
∧
∨
⊕
¬
( ), < >
Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers
(R0 to R7 and E0 to E7).
Rev. 3.00 Sep. 10, 2007 Page 459 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
