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HD64F36077G 参数 Datasheet PDF下载

HD64F36077G图片预览
型号: HD64F36077G
PDF下载: 下载PDF文件 查看货源
内容描述: 旧公司名称在产品目录等资料 [Old Company Name in Catalogs and Other Documents]
分类和应用:
文件页数/大小: 566 页 / 3220 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Section 16 Serial Communication Interface 3 (SCI3)  
16.6.2  
Multiprocessor Serial Data Reception  
Figure 16.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in  
SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data  
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is  
generated at this time. All other SCI3 operations are the same as those in asynchronous mode.  
Figure 16.18 shows an example of SCI3 operation for multiprocessor format reception.  
Rev. 3.00 Sep. 10, 2007 Page 321 of 528  
REJ09B0216-0300  
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