Section 13 Timer Z
13.3.12 Timer Interrupt Enable Register (TIER)
TIER enables or disables interrupt requests for overflow or GR compare match/input capture.
Timer Z has two TIER registers, one for each channel.
Initial
Bit
Bit Name value
R/W
Description
7 to 5
All 1
0
Reserved
These bits are always read as 1.
Overflow Interrupt Enable
4
OVIE
R/W
0: Interrupt requests (OVI) by OVF or UDF flag are
disabled
1: Interrupt requests (OVI) by OVF or UDF flag are
enabled
3
2
1
0
IMIED
IMIEC
IMIEB
IMIEA
0
0
0
0
R/W
R/W
R/W
R/W
Input Capture/Compare Match Interrupt Enable D
0: Interrupt requests (IMID) by IMFD flag are disabled
1: Interrupt requests (IMID) by IMFD flag are enabled
Input Capture/Compare Match Interrupt Enable C
0: Interrupt requests (IMIC) by IMFC flag are disabled
1: Interrupt requests (IMIC) by IMFC flag are enabled
Input Capture/Compare Match Interrupt Enable B
0: Interrupt requests (IMIB) by IMFB flag are disabled
1: Interrupt requests (IMIB) by IMFB flag are enabled
Input Capture/Compare Match Interrupt Enable A
0: Interrupt requests (IMIA) by IMFA flag are disabled
1: Interrupt requests (IMIA) by IMFA flag are enabled
Rev. 3.00 Sep. 10, 2007 Page 220 of 528
REJ09B0216-0300
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