A.3 Treatment of Unused Pins ................................................................................................. 724
A.4 Pin States in Access to Each Address Space ..................................................................... 725
Appendix B Memory-Mapped Control Registers....................................................... 739
B.1 Register Address Map ....................................................................................................... 739
B.2 Register Bits ...................................................................................................................... 745
Appendix C Product Lineup............................................................................................. 757
Appendix D Package Dimensions................................................................................... 758
Rev. 5.00, 09/03, page xxx of xliv
RENESAS [ RENESAS TECHNOLOGY CORP ]
