15.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode .................... 507
15.4.2 Retransmission (Receive and Transmit Modes)................................................... 509
Section 16 Serial Communication Interface with FIFO (SCIF)............................. 511
16.1 Overview........................................................................................................................... 511
16.1.1 Features ................................................................................................................ 511
16.1.2 Block Diagram ..................................................................................................... 512
16.1.3 Pin Configuration ................................................................................................. 515
16.1.4 Register Configuration ......................................................................................... 516
16.2 Register Descriptions......................................................................................................... 517
16.2.1 Receive Shift Register (SCRSR).......................................................................... 517
16.2.2 Receive FIFO Data Register (SCFRDR).............................................................. 517
16.2.3 Transmit Shift Register (SCTSR)......................................................................... 517
16.2.4 Transmit FIFO Data Register (SCFTDR) ............................................................ 518
16.2.5 Serial Mode Register (SCSMR) ........................................................................... 518
16.2.6 Serial Control Register (SCSCR) ......................................................................... 520
16.2.7 Serial Status Register (SCSSR)............................................................................ 522
16.2.8 Bit Rate Register (SCBRR).................................................................................. 527
16.2.9 FIFO Control Register (SCFCR).......................................................................... 534
16.2.10 FIFO Data Count Register (SCFDR) ................................................................... 536
16.3 Operation........................................................................................................................... 537
16.3.1 Overview.............................................................................................................. 537
16.3.2 Serial Operation.................................................................................................... 538
16.4 SCIF Interrupts.................................................................................................................. 550
16.5 Usage Notes....................................................................................................................... 551
Section 17 IrDA.................................................................................................................... 555
17.1 Overview........................................................................................................................... 555
17.1.1 Features ................................................................................................................ 555
17.1.2 Block Diagram ..................................................................................................... 556
17.1.3 Pin Configuration ................................................................................................. 559
17.1.4 Register Configuration ......................................................................................... 560
17.2 Register Description.......................................................................................................... 561
17.2.1 Serial Mode Register (SCSMR) ........................................................................... 561
17.3 Operation Description ....................................................................................................... 563
17.3.1 Overview.............................................................................................................. 563
17.3.2 Transmitting ......................................................................................................... 563
17.3.3 Receiving.............................................................................................................. 564
Section 18 Pin Function Controller ................................................................................ 565
18.1 Overview........................................................................................................................... 565
18.2 Register Configuration ...................................................................................................... 569
18.3 Register Descriptions......................................................................................................... 570
Rev. 5.00, 09/03, page xxvi of xliv
RENESAS [ RENESAS TECHNOLOGY CORP ]
