Sleep to Power-On Reset
Reset
CKIO, CKIO2*7
RESETP*1
Normal*5
Sleep*4
Reset*3
Normal*5
2
STATUS
*
0 to 10 Bcyc*6
0 to 30 Bcyc*6
Notes: 1. When the PLL1’s multiplication ratio is changed by a power-on reset,
keep RESETP low during the PLL’s oscillation settling time.
2. Undefined
3. Reset:
4. Sleep:
HH (STATUS1 high, STATUS0 high)
HL (STATUS1 high, STATUS0 low)
5. Normal: LL (STATUS1 low, STATUS0 low)
6. Bcyc: Bus clock cycle
7. The CKIO2 output is available only in clock modes 0, 1, and 2.
Figure 8.8 Sleep to Power-On Reset STATUS Output
Rev. 5.00, 09/03, page 197 of 760