Table 8.1 Power-Down Modes
State
On-Chip
Reg- On-Chip Peripheral
CPG CPU ister Memory Modules
CPU
Transition
Conditions
External Canceling
Pins Memory Procedure
Mode
Sleep
mode
Execute SLEEP
instruction with
STBY bit cleared
to 0 in STBCR
Runs Halts Held Held
Run
Held Refresh
1. Interrupt
2. Reset
1
*
Standby Execute SLEEP
Halts Halts Held Held
Halt
Held Self-
refresh
1. Interrupt
2. Reset
mode
instruction with
STBY bit set to
1 in STBCR
2
*
Module
standby
function
Set MSTP bit to
1 in STBCR
Runs Runs Held Held
Specified
module
halts
Refresh
1. Clear MSTP
bit to 0
or
halts
2. Reset
3
*
Hardware Drive CA pin low Halts Halts Held Held
standby
mode
Halt
Held Self-
refresh
Power-on reset
Notes: 1. The RTC still runs if the START bit in RCR2 is set to 1 (see section 13, Realtime Clock
(RTC)). The TMU still runs when output of the RTC is used as input to its counter (see
section 12, Timer (TMU)).
2. Depends on the on-chip peripheral module.
TMU external pin: Held
SCI external pin: Reset
3. The RTC still runs if the START bit in RCR2 is set to 1. The TMU does not run.
Rev. 5.00, 09/03, page 182 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
