7.1.3
Register Configuration
Table 7.1 Register Configuration
Access
Size
1
*
Name
Abbr.
R/W
Initial Value
H'00000000
H'00000000
Address
Location
UBC
Break address register A
BARA
R/W
H'FFFFFFB0 32
H'FFFFFFB4 32
Break address mask
register A
BAMRA R/W
UBC
Break bus cycle register A
Break address register B
BBRA
BARB
R/W
R/W
H'0000
H'FFFFFFB8 16
H'FFFFFFA0 32
H'FFFFFFA4 32
UBC
UBC
UBC
H'00000000
H'00000000
Break address mask
register B
BAMRB R/W
Break bus cycle register B
Break data register B
BBRB
BDRB
R/W
R/W
H'0000
H'FFFFFFA8 16
H'FFFFFF90 32
H'FFFFFF94 32
H'FFFFFF98 32
H'FFFFFF9C 16
UBC
UBC
UBC
UBC
UBC
H'00000000
H'00000000
H'00000000
H'0000
Break data mask register B BDMRB R/W
Break control register
BRCR
BETR
R/W
R/W
Execution count break
register
2
*
Branch source register
BRSR
R
R
Undefined
Undefined
Undefined
Undefined
H'FFFFFFAC 32
H'FFFFFFBC 32
H'FFFFFFE4 16
H'FFFFFFE8 16
UBC
UBC
CCN
CCN
2
*
Branch destination register BRDR
Break ASID register A
Break ASID register B
BASRA R/W
BASRB R/W
Notes: 1. Initialized by power-on reset. Values held in standby state and undefined by manual
resets.
2. Bit 31 of BRSR and BRDR (valid flag) is initialized by power-on resets. But other bits
are not initialized.
Rev. 5.00, 09/03, page 151 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
