5.4.3
Examples of Usage
(1) Invalidating a Specific Entry
A specific cache entry can be invalidated by accessing the allocated memory cache and writing a 0
to the entry’s U and V bits. The A bit is cleared to 0, and an address is specified for the entry
address and the way. If the U bit of the way of the entry in question was set to 1, the entry is
written back and the V and U bits specified by the write data are written to.
In the following example, the write data is specified in R0 and the address is specified in R1.
; R0 = H'0000 0000 LRU = H'000, U = 0, V = 0
; R1 = H'F000 1080, Way = 1, Entry = H'08, A = 0
;
MOV.L R0, @R1
To invalidate all entries and ways, write 0 to the following addresses.
Addresses
F000 0000
F000 0010
F000 0020
:
F000 3FF0
This involves a total of 1,024 writes.
The above operation should be performed using a non-cacheable area.
(2) Invalidating a Specific Address
A specific address can be invalidated by writing a 0 to the entry’s U and V bits. When the A bit is
1, the tag address specified by the write data is compared to the tag address within the cache
selected by the entry address. If the tag addresses match, data is written to the memory at that
address. If no match is found, no operation is carried out. If the entry’s U bit is 1 at that time, the
entry is written back.
; R0 = H'0110 0010; Tag address = B'0000 0001 0001 0000 0000 00, U = 0,
V = 0
; R1 = H'F000 0088; Address array access, Entry = H'08, A = 1
;
MOV.L R0, @R1
Rev. 5.00, 09/03, page 115 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
