(1) TLB Address Array Access
Read access
6
31
31
24 23
17 16
12 11 10 9 8 7
0
Address field
Data field
0
11110010
VPN
W
* *
*
*
*
*
17
16
0
12 11 10 9 8 7
0 VPN 0 V
0
VPN
ASID
Write access
Address field
31
31
24 23
17 16
6
0
12 11 10 9 8 7
11110010
VPN
W
0
* *
*
*
*
*
17 16
12 11 10 9 8 7
VPN
0
Data field
VPN
V
ASID
*
*
*
VPN: Virtual page number
V: Valid bit
W: Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
ASID: Address space identifier
Don't care bit
:
*
(2) TLB Data Array Access
Read/write access
12 11 10 9 8 7
31
24 23
17 16
0
Address field
Data field
11110011
VPN
W
* *
*
*
*
*
31 29 28
000
10 9
8
7 6 5 4
3
2
1
0
PPN
X
V X PR SZ C D SH X
PPN: Physical page number
PR: Protection key field
C: Cacheable bit
V: Valid bit
SZ: Page-size bit
D: Dirty bit
*
Don't care bit
SH: Share status bit
VPN: Virtual page number
:
X: 0 for read, don’t care bit for write
W: Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
Figure 3.14 Specifying Address and Data for Memory-Mapped TLB Access
Rev. 5.00, 09/03, page 82 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
