5. The MMU control register (MMUCR) residing at address H'FFFFFFE0, which makes the
MMU settings described in figure 3.3. Any program that modifies MMUCR should reside in
the P1 or P2 area.
The MMU registers are shown in figure 3.3.
31
10
7
0
0
VPN
0
ASID
PTEH
PTEL
31 29 28
000
10 9 8 7 6
4 3 2 1
0 V* 0 PR* SZ* C D* SH* 0
*
PPN
31
0
TTB
TTB
31
0
Virtual address causing TLB-related
or address error exception
TEA
31
8
7 6 5 4 3 2
1
0
0
SV 00 RC 0 TF IX AT
MMUCR
0: Reserved bits. Always read as 0. Writing is ignored. However, 0 should also be
specified in a write to MMUCR only.
SV: Single virtual memory mode bit. 0: Multiple virtual memory mode
1: Single virtual memory mode
RC: A 2-bit random counter, automatically updated by hardware according to the
following rules in the event of an MMU exception. When a TLB miss exception
occurs, all TLB entry ways corresponding to the virtual address at which the
exception occurred are checked, and if all ways are valid, 1 is added to RC; if
there is one or more invalid way, they are set by priority from way 0, in the order:
way 0, way 1, way 2, way 3. In the event of an MMU exception other than a TLB
miss exception, the way which caused the exception is set in RC.
TF: TLB flush bit. Write 1 to flush the TLB (clear all valid bits of the TLB to 0). Always
reads 0.
IX: Index mode bit. When 0, VPN bits 16−12 are used as the TLB index number.
When 1, the value obtained by EX-ORing ASID bits 4−0 in PTEH and VPN bits
16−12 are used as the TLB index number.
AT: Address translation bit. Enables/disables the MMU.
0: MMU disabled
1: MMU enabled
Note: * Refer to section 3.3, TLB Functions.
Figure 3.3 MMU Register Contents
Rev. 5.00, 09/03, page 62 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
