3.1.4
Register Configuration
A register that has an undefined initial value must be initialized by software. Table 3.1 shows the
configuration of the MMU control registers.
Table 3.1 Register Configuration
Initial
Value
1
*
Name
Abbreviation R/W
Size
Address
Page table entry register high
Page table entry register low
Translation table base register
TLB exception address register
MMU control register
PTEH
PTEL
TTB
R/W
R/W
R/W
R/W
R/W
Longword Undefined H'FFFFFFF0
Longword Undefined H'FFFFFFF4
Longword Undefined H'FFFFFFF8
TEA
Longword Undefined H'FFFFFFFC
2
*
MMUCR
Longword
H'FFFFFFE0
Notes: 1. Initialized by a power-on reset or manual reset.
2. SV bit: undefined
Other bits: 0
3.2
Register Description
There are five registers for MMU processing. These registers are located in address space area P4
and can only be accessed from privileged mode by specifying the address.
1. The page table entry register high (PTEH) register residing at address H'FFFFFFF0, which
consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the virtual
address at which the exception is generated in case of an MMU exception or address error
exception. When the page size is 4 kbytes, the VPN is the upper 20 bits of the virtual address,
but in this case the upper 22 bits of the virtual address are set. The VPN can also be modified
by software. As the ASID, software sets the number of the currently executing process. The
VPN and ASID are recorded in the TLB by the LDTLB instruction.
2. The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to
store the physical page number and page management information to be recorded in the TLB
by the LDTLB instruction. The contents of this register are only modified in response to a
software command. (Refer to section 3.4.3, MMU Instruction (LDTLB), and section 3.5,
MMU Exceptions.)
3. The translation table base register (TTB) residing at address H'FFFFFFF8, which points to the
base address of the current page table. The hardware does not set any value in TTB
automatically. TTB is available to software for general purposes.
4. The TLB exception address register (TEA) residing at address H'FFFFFFFC, which stores the
virtual address corresponding to a TLB or address error exception. This value remains valid
until the next exception or interrupt.
Rev. 5.00, 09/03, page 61 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
