Table A.1 Address List (cont)
Synchro-
nization
Sleep Standby Clock
Area 7
Power-On
Size Reset
Manual
Reset
1
*
Module Register P4 Address Address
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
WCR3
MCR
H'FF80 0010 H'1F80 0010 32
H'FF80 0014 H'1F80 0014 32
H'FF80 0018 H'1F80 0018 16
H'FF80 001C H'1F80 001C 16
H'FF80 0020 H'1F80 0020 16
H'FF80 0024 H'1F80 0024 16
H'FF80 0028 H'1F80 0028 16
H'FF80 002C H'1F80 002C 32
H'FF80 0030 H'1F80 0030 16
H'FF80 0040 H'1F80 0040 32
H'FF80 0044 H'1F80 0044 16
H'FF80 0048 H'1F80 0048 16
H'0777 7777 Held
H'0000 0000 Held
Held Held
Held Held
Held Held
Held Held
Held Held
Held Held
Held Held
Held Held
Held Held
Held Held
Held Held
Held Held
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
PCR
H'0000
H'0000
H'0000
H'0000
H'0000
Held
Held
Held
Held
Held
RTCSR
RTCNT
RTCOR
RFCR
PCTRA
PDTRA
PCTRB
PDTRB
GPIOIC
SDMR2
SDMR3
H'0000 0000 Held
Undefined Held
H'0000 0000 Held
Undefined Held
H'0000 0000 Held
Write-only
H'FF90 xxxx H'1F90 xxxx
H'FF94 xxxx H'1F94 xxxx
8
8
DMAC SAR0
DMAC DAR0
H'FFA0 0000 H'1FA0 0000 32
H'FFA0 0004 H'1FA0 0004 32
Undefined
Undefined
Undefined
Undefined
Held Held
Held Held
Held Held
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Bclk
Undefined
Undefined
DMAC DMATCR0 H'FFA0 0008 H'1FA0 0008 32
DMAC CHCR0
DMAC SAR1
DMAC DAR1
H'FFA0 000C H'1FA0 000C 32
H'FFA0 0010 H'1FA0 0010 32
H'FFA0 0014 H'1FA0 0014 32
H'0000 0000 H'0000 0000 Held Held
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Held Held
Held Held
Held Held
DMAC DMATCR1 H'FFA0 0018 H'1FA0 0018 32
DMAC CHCR1
DMAC SAR2
DMAC DAR2
H'FFA0 001C H'1FA0 001C 32
H'FFA0 0020 H'1FA0 0020 32
H'FFA0 0024 H'1FA0 0024 32
H'0000 0000 H'0000 0000 Held Held
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Held Held
Held Held
Held Held
DMAC DMATCR2 H'FFA0 0028 H'1FA0 0028 32
DMAC CHCR2
DMAC SAR3
DMAC DAR3
H'FFA0 002C H'1FA0 002C 32
H'FFA0 0030 H'1FA0 0030 32
H'FFA0 0034 H'1FA0 0034 32
H'0000 0000 H'0000 0000 Held Held
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Held Held
Held Held
Held Held
DMAC DMATCR3 H'FFA0 0038 H'1FA0 0038 32
DMAC CHCR3
DMAC DMAOR
H'FFA0 003C H'1FA0 003C 32
H'FFA0 0040 H'1FA0 0040 32
H'0000 0000 H'0000 0000 Held Held
H'0000 0000 H'0000 0000 Held Held
Rev. 6.0, 07/02, page 938 of 986