Table A.1 Address List (cont)
Synchro-
nization
Sleep Standby Clock
Area 7
Power-On
Size Reset
Manual
Reset
1
*
Module Register P4 Address Address
2
2
2
2
*
*
*
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RHRAR
RWKAR
H'FFC8 0028 H'1FC8 0028 8
H'FFC8 002C H'1FC8 002C 8
Held
Held
Held
Held
Held
Held
Held
Held Held
Held Held
Held Held
Held Held
Held Held
Held Held
Held Held
Held Held
Pclk
Pclk
Pclk
Pclk
Pclk
Pclk
Pclk
Pclk
RDAYAR H'FFC8 0030 H'1FC8 0030 8
RMONAR H'FFC8 0034 H'1FC8 0034 8
*
Held
2
2
*
*
RCR1
RCR2
RCR3
H'FFC8 0038 H'1FC8 0038 8
H'FFC8 003C H'1FC8 003C 8
H'FFC8 0050 H'1FC8 0050 8
H'FFC8 0054 H'1FC8 0054 16
H'00
H'09
H'00
H'00
H'00
Held
2
2
*
*
5
*
5
*
RYRAR
Undefined
Held
2
2
*
*
INTC
INTC
INTC
INTC
INTC
INTC
ICR
H'FFD0 0000 H'1FD0 0000 16
H'FFD0 0004 H'1FD0 0004 16
H'FFD0 0008 H'1FD0 0008 16
H'FFD0 000C H'1FD0 000C 16
H'FFD00010 H'1F000010 16
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
Held Held
Held Held
Held Held
Held Held
Held Held
Held Held
Pclk
Pclk
Pclk
Pclk
Pclk
Pclk
IPRA
IPRB
IPRC
4
*
IPRD
H'DA74
H'DA74
INTPRI00 H'FE08 0000 H'1E08 0000 32
H'0000 0000 Held
H'0000 0000 Held
H'0000 0300 Held
Write-only
5
*
INTC
INTC
INTC
INTREQ00 H'FE08 0020 H'1E08 0020 32
Held Held
Held Held
Pclk
Pclk
Pclk
5
*
INTMSK00 H'FE08 0040 H'1E08 0040 32
5
*
INTMSKCL H'FE08 0060 H'1E08 0060 32
R00
5
*
6
6
*
CPG
CLKSTP00 H'FE0A 0000 H'1E0A 0000 32
*
H'0000 0000 Held
Write-only
Held Held
Pclk
Pclk
5
*
CPG
CLKSTPC H'FE0A 0008 H'1E0A 0008 32
5
*
LR00
5
*
TMU
TMU
TMU
TMU
TMU
TMU
TMU
TSTR2
H'FE10 0004 H'1E10 0004 8
H'FE10 0008 H'1E10 0008 32
H'FE10 000C H'1E10 000C 32
H'FE10 0010 H'1E10 0010 16
H'FE10 0014 H'1E10 0014 32
H'FE10 0018 H'1E10 0018 32
H'FE10 001C H'1E10 001C 16
H'00
Held
Held Held
Held Held
Held Held
Held Held
Held Held
Held Held
Held Held
Pclk
Pclk
Pclk
Pclk
Pclk
Pclk
Pclk
5
*
TCOR3
H'FFFF FFFF Held
H'FFFF FFFF Held
5
*
TCNT3
5
*
TCR3
H'0000
Held
5
*
TCOR4
H'FFFF FFFF Held
H'FFFF FFFF Held
5
*
TCNT4
5
*
TCR4
H'0000
Held
Rev. 6.0, 07/02, page 940 of 986